Switching arrangements for driving a load frequently include at least one pair of switching transistors, which are field effect transistors coupled in series between a supply voltage and ground. For example, one such switching arrangement includes a first pair of field effect switching transistors coupled in series between a supply voltage and ground, and includes a second pair of field effect switching transistors also coupled in series between the supply voltage and ground. A load has a first end coupled to the node between the transistors of the first pair, and a second end coupled to the node between the transistors of the second pair. This exemplary arrangement of two transistor pairs and a load is commonly known as an H-bridge configuration. When a switching transistor pair of this type is implemented in an integrated circuit, the structure of the implementation can inherently create unwanted parasitic circuit devices, such as diodes and/or transistors.
For example, one integrated circuit for implementing a switching transistor pair includes a P-epi substrate having first and second n+ isolation layers buried therein. First and second portions of the P-epi substrate are disposed within the first and second isolation layers. The first and second portions each have therein a p-well containing a source region, and an n-type drain region spaced from the p-well. The drain region in the second portion is coupled to a supply voltage, the source region in the second portion is coupled to the drain region in the first portion, and the source region in the first portion is coupled to ground. The substrate is coupled to ground at a contact region external to both isolation regions, and the isolation regions are both coupled to the supply voltage. The source and drain regions for the first portion must both be spaced from the isolation region for the first portion, in order to avoid breakdown.
In this integrated circuit, the drain region in the first portion, the first portion itself and the first isolation layer together act as an NPN bipolar junction transistor. Since the collector (first isolation layer) is coupled to a supply voltage, and since the base is lightly doped (P-epi), when the base-emitter junction of this parasitic NPN transistor is forward biased, there will be a high gain and a substantial amount of current flow in the collector, causing the parasitic transistor to dissipate substantial power. Since the parasitic transistor is unnecessary to the operation of the switching transistor pair, its power dissipation represents undesirable inefficiency.
A further consideration results from the fact that the first isolation layer is coupled to the supply voltage, whereas the source region of the first portion and a contact region of the substrate are both coupled to ground. In order to avoid breakdown, the source region of the first portion and the contact region of the substrate must both be spaced adequately from the first isolation layer. Due in part to this requirement, the die area required to implement the switching transistor pair in the integrated circuit is larger than desirable. In view of the fact that cost is an important factor in the manufacture and sale of integrated circuits, and the fact that cost is related to die area, reducing the die area is advantageous.